1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the same, and is applied to, for example, a select transistor for selecting memory cell transistors having current paths connected in series in a NAND type flash memory.
2. Description of the Related Art
With ever increasing development in fine patterning of cells, there is a tendency that contacts for electrically connecting, e.g. diffusion layers of cells become still finer. Furthermore, with the progress of the generation of cells, it becomes difficult to carry out microfabrication of contacts by so-called lithography technology.
Jpn. Pat. Appln. KOKAI Publication No. 2002-118166, for instance, discloses a method wherein an etching mask film 13a, which has an opening pattern corresponding to a pattern of a diffusion layer 7 that serves as a source/drain, is formed on a first insulation film 11. Using the etching mask film 13a as a mask, the first insulation film 11 is etched down to a level of the surface of a silicide layer 8 that lies on the diffusion layer 7. Thus, a contact hole 14a is formed on the diffusion layer 7.
With this method, however, if the controllability of the etching step is inadequate, the silicide layer 8 on the diffusion layer 7 would be etched, or non-uniformity would occur in resistance value of the silicide layer 8 from cell to cell, due to a reaction between the silicide layer 8 and a gate insulation layer 2. Consequently, the reliability of the device deteriorates.
In addition, there is a tendency that the conventional structure, wherein the silicide layer 8 is provided on the diffusion layer 7, is disadvantageous for fine patterning for the following reasons (1) and (2).
(1) If the silicide layer 8 and gate insulation film 2 are provided close to each other, a substance (e.g. cobalt) in the silicide layer 8 would affect the film quality of the gate insulation film 2, and the insulation properties would deteriorate. Consequently, the reliability of the device would lower.
(2) The silicide layer 8 on the diffusion layer causes so-called junction leak.
In addition, the silicide layer 8 on the diffusion layer 7 reacts with the gate insulation film 2, thereby causing short-circuit between the silicide layer 8 and a gate electrode 6. As a result, the insulation properties would be degraded.
As has been described above, the conventional semiconductor device is disadvantageous for fine patterning, and the silicide layer on the diffusion layer reacts with the gate insulation film, thereby causing short-circuit between the silicide layer and gate electrode. Consequently, the insulation properties become poor and the reliability deteriorates.
Besides, in the method of manufacturing the conventional semiconductor device, if the controllability of the etching step is inadequate, the silicide layer on the diffusion layer would be etched, or non-uniformity would occur in resistance value of the silicide layer from cell to cell due to a reaction between the silicide layer and gate insulation layer. Consequently, the reliability of the device deteriorates.